[llvm-dev] [GlobalISel] Quick Status

[Renato Golin via llvm-dev]

Hi Quentin,

Thanks for the summary. I will indeed do my best to get the wider community
together. Some of the people there are already volunteering, so we should
be fine.

Cheers,
Renato

On 13 Feb 2017 16:23, "Quentin Colombet" <qcolombet at apple.com> wrote:

> Hi all,
>
> We’ve been discussing offline some important points that I believe are
> useful to clarify on the mailing list as well, so here they are!
>
>
> *** What do we need to complete so we can declare GISel “production
> quality"? "Default ISel in O0”? ***
>
> First, we are going to add O0 bots to make sure we catch the problem sas
> early as possible. We actually already have such bots internally.
>
> From our perspective, we won’t suggest to flip the switch until we
> successfully hit those milestones:
> - LLVM test suite + external
> - Self host + test-suite again
> - Internal test cases
> - World build
>
> Moreover, we acknowledge that the LLVM test-suite and `make check` are not
> good enough to test the coverage of a new ISel. Therefore, as we bring up
> GISel, we also push on the infrastructure to improve the testing story.
> In particular, we are working on:
> - Tests generated from the tablegen inputs
> - Fuzzer for instruction selection
> - Better and more unit tests
>
> Second the switch to have GISel being the default ISel at O0 is an ongoing
> discussion with the community, we won’t make that decision alone!
>
> Moreover, we would like to get help and feedback from the following
> communities/users to make sure we cover as much use cases as possible
> upfront:
> A. FreeBSD
> B. Linux (both Debian and OpenMandriva)
> C. Android
> D. Chromium
>
> I don’t want to put words in Renato’s mouth, but my understanding is he’s
> going to help to get the right people in those communities involved.
>
> Finally, for the first year of living on GISel at O0, we plan to keep the
> fallback path to SDISel. That won’t help us with miscompile, but that will
> ensure we don’t abort on missing coverage if any. We see all those
> miscompile/crashes as showstopper and will actively working on fixing them.
>
> The bottom line is please play with GISel and file PRs for the cases that
> are interesting to you and don't work.
> Note: We are not in that code quality yet (right now we are in a
> coverage/correctness focus), but we aim at generating the same code quality
> as SDISel. When we switch to this “code quality” focus, we will want your
> feedback on that too!
>
>
> *** How to avoid Global ISel being a replacement for just Fast ISel? ***
>
> Given we aim at replacing O0 at first, you might be worried that GISel is
> going to be a FastISel only replacement. This is clearly not the goal.
>
> We are actually working towards the O1/O2/O3 replacement as well in
> parallel, hence all the work that you may have noticed regarding reusing
> the existing SDISel patterns in GISel. The reason we are not making any
> claims is that we don’t know what the timeline is going to look like.
>
>
> *** How do we make sure the experience for debugging remains as good as
> what SDISel/FastISel were offering? ***
>
> O0 is important to debugging code and we need to account for that in GISel
> as well.
>
> For this part, we involved and rely on our debug experts to do the
> testing. In particular Adrian is working on a Dwarf verifier IIRC that we
> are going to use to check that the generated debug info are in line with
> the previous ISels.
>
> Obviously this part of the project will benefit from all the help we can
> get. Kristof (Beyls) is also going to work with their gdb and DS-5 debug
> experts on the testing.
>
> The main issue really is that we don’t think anyone has an idea on what a
> good infrastructure should be for this problem.
>
>
> If you plan to help or have ideas on any of those points, let me know.
>
> Thanks,
> -Quentin
>
>
> > On  Jan 20, 2017, at 5:19 PM, Quentin Colombet via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
> >
> > Hi all,
> >
> > Following the thread from http://lists.llvm.org/pipermail/llvm-dev/2017-
> January/109029.html, I am sending this email to give a status on
> GlobalISel progress and situation.
> >
> > We are pushing GlobalISel from the state of prototype to a production
> quality framework. We welcome help with patches, reviews, feedbacks and so
> on.
> >
> > As explained during the last developer meeting, we are aiming at
> enabling GISel by default for AArch64 at -O0 for this year (See
> http://llvm.org/devmtg/2016-11/#talk16).
> >
> > Note: That does not mean the design is settle nor that we won’t change
> the APIs.
> > Note: A lot of the things listed in this email is a reminder of what we
> said during the dev meeting talk.
> >
> > *** High Level View ***
> >
> > As of r292481, we compile and run correctly with GISel (without fall
> back to SDISel) 63% of the LLVM test suite. If you are interested in
> detailed numbers, please see the attachments (courtesy of Kristof Beyls).
> >
> > Note: The compile time numbers are probably noisy (compiled in parallel
> on the same machine), and not relevant at this point of the project anyway.
> >
> >
> > *** Per Pass Status ***
> >
> > ** IRTranslator **
> >
> > Mostly done.
> >
> > * What’s Left? *
> >
> > Some instructions are not yet supported.
> >
> >
> > ** Legalizer **
> >
> > Core logic is present.
> >
> > * What’s Left? *
> >
> > - A lot of instructions are missing, in particular the vector ones.
> > - Legalization of G_SEQUENCE/G_EXTRACT still up in the air for complex
> cases.
> >
> > Note: The lack of broad vector support is one on the reason we target
> O0, i.e., the vectorizer doesn’t run and we are less likely to hit the
> missing implementation.
> >
> >
> > ** RegBankSelect **
> >
> > - Core logic is present, no optimizations yet, or more accurately, the
> greedy mode is still pretty silly.
> > - TableGen support for RegisterBanks description.
> >
> > * What’s Left *
> >
> > - TableGen the instruction mapping from the existing SDISel patterns.
> > - Improve the optimization heuristic.
> >
> >
> > ** InstructionSelect **
> >
> > - Core logic present.
> > - TableGen support for simple SDISel patterns (i.e., GISel reuses SDISel
> patterns)
> >
> > * What’s Left *
> >
> > - Teach TableGen how to reuse more complex patterns:
> > — Patterns with combines in them (e.g., (mull (add)) => madd)
> > — Patterns with complex patterns (e.g., SelectAddressModXR0)
> >
> >
> > *** On Going Work ***
> >
> > - General approach: use AArch64 O0 on the LLVM test suite as a driving
> vehicle to guide what to support next in the various passes.
> > - Extend TableGen support to reuse more and more SDISel patterns.
> > - ARM port.
> > - AMDGPU port.
> > - X86 port.
> >
> > If you have questions, don’t hesitate!
> >
> > Cheers,
> > -Quentin
> > <292481_gisel_testsuite_status.xlsx>__________________
> _____________________________
> > LLVM Developers mailing list
> > llvm-dev at lists.llvm.org
> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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