[llvm-dev] RFC: Generic IR reductions

Renato Golin via llvm-dev llvm-dev at lists.llvm.org
Wed Feb 1 02:59:17 PST 2017

On 1 February 2017 at 08:27, Renato Golin <renato.golin at linaro.org> wrote:
> Sorry, I meant min/max + reduce, just like above.
>   %sum = add <N x float>, <N x float> %a, <N x float> %b
>   %min = @llvm.minnum(<N x float> %sum)
>    %red = @llvm.reduce(%min, float %acc)

No, this is wrong. I actually meant overriding the max/min intrinsics
to take vectors instead of two scalar options.

The semantics of those intrinsics is to get a number of parameters and
return the max/min on their own type. A vector is just a different
packing of parameters, all of which have the same type, so there's no
semantic difference other than the number of arguments.

However, when they're lowered, they'll end up a a short sequence of
instruction (if supported) in the same way.

You'd only emit a max/min in vectorisation if the target supports it
and the cost is low. For instance, in AArch64 it would only emit it if
SVE support is enabled.

Makes sense?


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