[llvm-dev] Canonical way to handle zero registers?

Sean Silva via llvm-dev llvm-dev at lists.llvm.org
Thu Dec 28 18:02:42 PST 2017


On Dec 27, 2017 2:00 PM, "Matt Arsenault" <arsenm2 at gmail.com> wrote:



> On Dec 26, 2017, at 18:42, Sean Silva via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
>
> Thanks! That looks like a winning approach.
>
> I swear I grepped around for ISD::Constant but for some reason never
found this code. I think maybe I was searching for ISD::Constant with
setOperationAction, which in hindsight was narrowing down my search to just
lowering, which is exactly what I didn't want! (I was looking for other
approaches). I also tried looking in depth at PowerPC but it looks like it
doesn't use this approach either.
>
> -- Sean Silva

What’s the reason for trying to handle this in SelectionDAG at all? I would
just materialize zero like any other constant, and treat replacing that
with the zero register as an immediate folding optimization (e.g.
FoldImmediate or another peephole pass)


I thought about doing that, but I wasn't sure I could make it work.

The issue is that the hardwired registers are actually the only way to
write immediates of this register class (the registers are very small,
obviously). I've been phrasing this as integer 0 (and -1) to keep the
discussion closer to other architectures, but the fact that these hardwired
registers are the only way to reference immediates of this register class
is one important difference.

One thing I've been curious about is how immediates interact with register
classes. Could we use ordinary immediate MachineOperand's (of the
appropriate bit width) and just print the immediate MO's of this register
class as the corresponding hardwired register? Does MIR have any
constraints on using an immediate MO instead of a register?

-- Sean Silva


-Matt
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