[llvm-dev] Register Allocation Graph Coloring algorithm and Others

Matthias Braun via llvm-dev llvm-dev at lists.llvm.org
Tue Dec 19 12:24:05 PST 2017



> On Dec 18, 2017, at 8:16 PM, Vladimir Makarov via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> 
> 
> On 12/18/2017 07:07 PM, Michael Clark wrote:
>> Hi Leslie,
>> 
>> I suggest adding these 3 papers to your reading list.
>> 
>> 	Register allocation for programs in SSA-form
>> 	Sebastian Hack, Daniel Grund, and Gerhard Goos
>> 	http://www.rw.cdl.uni-saarland.de/~grund/papers/cc06-ra_ssa.pdf
>> 
>> 	Simple and Efficient Construction of Static Single Assignment Form
>> 	Matthias Braun , Sebastian Buchwald , Sebastian Hack , Roland Leißa , Christoph Mallon , and Andreas Zwinkau
>> 	https://www.info.uni-karlsruhe.de/uploads/publikationen/braun13cc.pdf
>> 
>> 	Optimal register allocation for SSA-form programs in polynomial time
>> 	Sebastian Hack, Gerhard Goos
>> 	http://web.cs.ucla.edu/~palsberg/course/cs232/papers/HackGoos-ipl06.pdf
>> 
>> A lot of the earlier literature regarding the register allocation problem describes the general graph colouring problem as NP-complete, however previous research in Register Allocation has been in the context of programs that were not in SSA form. i.e. the Chaitin-Briggs paper states that register allocation is NP-complete and proposes an iterative algorithm.
>> 
>> 
> I am sceptical about SSA-register allocators for high quality code generation.  But I should acknowledge although I tried a lot of RA algorithms I never tried SSA one.
> 
> One task of RA is to deal with moves but when you are destroying SSA you are creating moves or swaps.  Of course there are optimizations to decrease its number when you are going out of SSA.  But IMHO a good RA should see all moves created before or during own work.
> 
> As I already wrote coloring is just one out of many task of RA.  All these tasks in a good RA should be solved in cooperation. Optimistic coloring is good and fast enough (although building a conflict graph for it takes a lot of time).  I think better results can be obtained by improving other tasks than by improving optimistic coloring.
> 
> For example, nobody mentioned irregular file architectures (with subregisters and register subclasses) like x86/x86-64.  Even regular file architectures with caller/callee saved hard registers have irregularity because it creates register subclasses, e.g. class of saved general registers is a subclass of the overall general register class.  Usually hard registers are present in IR and if some pseudos conflict with the hard registers, it also create a lot (intersected) subclasses.

I’m not sure this is the best place to start a discussion about register allocation in general, but I’ll bait :)

Having worked with SSA regalloc in the past (and with LLVM now) I have to defend it: You can (and should) apply post-realloc copy coalescing algorithms for SSA allocators. The additional copies are a good thing, they are the reason for a less constrained graph with reduced register pressure meaning you can get by with less spills and reloads. Trading spills/reloads for copies is a good deal on most modern architectures.

And I would take your statement that “a good RA should see all moves created before or during own work” as an endorsement of SSA regallocs: PHIs are just another form of COPY and very visible and SSA allocators cannot do pre-RA coalescing (of the phi induced copies) so they will see all the copies.

SSA regalloc can handle classes/constraints just fine (you need to insert some more copies, but that is also true for most traditional reallocs). You are right in that SSA regalloc cannot directly deal with sub registers. I implemented support for that via a pre-pass in the past that merges subvalues before regalloc to get a regular regalloc problem again, which may be a bit tricky to pull off when your target has additional register constraints at the same time (which wasn’t the case for me). But for typical CPUs SSA regalloc is just fine: Libfirm where a lot of the SSA regalloc work happened sports high quality x86/x86_64/sparc code generators.

And I also agree that coloring is only part of the problem and while it is the most researched talked about, I would also say that in practice spill code placement, tweaks in your representation, how to deal with two address code and other constraints, how good your dematerialization is etc. has a bigger impact than your particular choice of coloring algorithm. And for regular architectures I found SSA to make things easier :)

- Matthias
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