[llvm-dev] Immediates in intrinsics

[Nemanja Ivanovic via llvm-dev]

If it's any easier Justin,
there are plenty of examples in the PPC back end already. Take for example
`int_ppc_vsx_xxinsertw`.

On Mon, Dec 18, 2017 at 2:47 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> To add to this: it is the "imm:$trap" in the selection pattern that does
> it (the "imm:" part of it, to be even more specific).
>
> -Krzysztof
>
>
> On 12/17/2017 11:01 PM, Craig Topper via llvm-dev wrote:
>
>> The fact that the intrinsic takes an immediate is usually encoded as part
>> of the isel pattern selection
>>
>> For example from an x86 intrinsic/instruction:
>>
>> def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
>>                [(int_x86_int imm:$trap)], IIC_INT>;
>>
>> I'm slightly confused by your question though as you mention register
>> which sort of implies you're looking at PowerPC assembly. But you also
>> mention a function, but the intrinsic should have been turned into
>> instructions before assembly and there should be no function call.
>>
>> ~Craig
>>
>> On Sun, Dec 17, 2017 at 8:26 PM, Justin Hibbits via llvm-dev <
>> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>
>>     I'm trying to add intrinsics for the Signal Processing Engine
>>     (FPU/vector unit) on some PowerPC cores, but running into a problem.
>>     Some of the instructions take an immediate operand, but I can't figure
>>     out how to make the intrinsic use an immediate, it just wants to load
>>     a register as an argument to the function.  Is there any way in the
>>     .td file to describe the intrinsic as taking an immediate, or do I
>>     need to generate an intermediate instruction identifier?
>>
>>     Thanks,
>>     Justin
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>>
>>
>>
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>>
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