[llvm-dev] Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'

[David Chisnall via llvm-dev]

On 24 Aug 2017, at 11:20, Martin J. O'Riordan <MartinO at theheart.ie> wrote:
> 
> Seems simple enough, no?  The object being to have a single definitive statement of the machine, and from that derive the RTL, silicon, documentation, assembler, compiler, debugger, simulator, etc.  It’s a neat objective, but not well realised.
> 
> There have been attempts in the past, but they always seem to fizzle out after a while, often because they begin as University PhD research topics, and after the original dissertation is completed, they just seem to die.

The Synopsis toolchain with their Lisa HDL can generate a TableGen back end for LLVM from the instruction descriptions.

David