[llvm-dev] RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends

[Alex Bradbury via llvm-dev]

On 21 August 2017 at 15:32, Alex Bradbury <asb at asbradbury.org> wrote:
> On 21 August 2017 at 11:53, Daniel Sanders <daniel_l_sanders at apple.com> wrote:
>> One thing to be aware of with this is that (IIRC) tablegen uses the pattern to infer things about the pattern. One example I vaguely remember is that an empty pattern would result in the same effect as hasSideEffects=1 and I think there were others.
>
> Thanks for the note - excellent point. Looking at
> CodeGenDAGPatterns.cpp, it seems in the absence of a pattern
> hasSideEffects will be 1, while mayLoad and mayStore default to 0.
> Back in 2012, Jakob Stoklund Olesen added the
> guessInstructionProperties flag, which causes an error
> <https://reviews.llvm.org/rL162460> if a property isn't set explicitly
> and can't be inferred. It doesn't look like any other in-tree targets
> have ended up enabling this, but it looks like it would be worth
> enabling for RISCV, particularly if going ahead with splitting
> instructions and patterns.

To updated on this, I've found guessInstructionProperties requires the
standard TargetOpcode::* instructions to have their properties
explicitly set. https://reviews.llvm.org/D37065 does this. If anyone
has any insight in to why TargetOpcode::PHI must have hasSideEffects
set, that would be interesting.

Best,

Alex