[llvm-dev] callee saved regs list

[Jonas Paulsson via llvm-dev]

Hi,

It has been discovered recently that it is needed for the SystemZ 
backend to add super-regs to the callee saved regs list like:

  def CSR_SystemZ : CalleeSavedRegs<(add (sequence "R%dD", 6, 15),
-                                       (sequence "F%dD", 8, 15))>;
+                                       [R6Q, R8Q, R10Q, R12Q, R14Q],
+                                       (sequence "F%dD", 8, 15),
+                                       [F8Q, F9Q, F12Q, F13Q])>;

(Q => 128 bits)

It seems strange that the common code cannot deduce for itself that the 
super regs are also callee saved given that all sub-regs of a register are.

Are other targets adding super-regs as well like this? Could / should 
this be fixed?

Thanks to Wei Mi for helping to point this out.

/Jonas