[llvm-dev] Mischeduler: Unknown reason for peak register pressure increase

[Kerbow, Austin Michael via llvm-dev]

Thank you for your answers! I am essentially trying to mimic the behavior of LLVM's register pressure tracker within our combinatorial scheduler. To do this I am collecting register Def/Use information using llvm::RegisterOperands, and finding LiveIn/LiveOut registers using llvm::ScheduleDAGMILive.RegPressure.LiveIn/LiveOut. When a register with some register class is live in our scheduler, we increase the current pressure in the corresponding pressure sets by the weight of the register class. When using this method, for most scheduling regions the peak register pressure for each pressure set match in our scheduler and in the mischeduler. However, in approximately 1 in 10 scheduling regions we are seeing a mismatch between our peak pressure values per-PSet and the values from the mischeduler. Below is a region with this type of mismatch. As an example, the PSset GR8_ABCD_L has a peak value of 1. However I don't see that this PSet is associated with any register class that is an operand of any instruction in the region nor do I see anything about this PSet in the Pressure Diff printouts. There are also no live-in registers that I can see. Do you have any ideas about what could be missing in our implementation?

These are some of the PSets missing pressure increases for in our implementation for this region.


SU(0):   %vreg2<def> = MOVSDrm %RIP, 1, %noreg, <cp#0>, %noreg; mem:LD8[ConstantPool] FR64:%vreg2
  # preds left       : 0
  # succs left       : 1
  # rdefs left       : 0
  Latency            : 4
  Depth              : 0
  Height             : 4
  Successors:
   data SU(2): Latency=4 Reg=%vreg2
  Pressure Diff      : FR32 -1    FR32X -1

SU(1):   %EDI<def,dead> = MOV32ri64 <ga:@_ZSt4cout>, %RDI<imp-def>
  # preds left       : 0
  # succs left       : 1
  # rdefs left       : 0
  Latency            : 1
  Depth              : 0
  Height             : 1
  Successors:
   ord  SU(4294967295) *: Latency=1
  Pressure Diff      : GR64_NOREX_and_GR64_TC -1    LOW32_ADDR_ACCESS_with_sub_32bit+GR64_NOREX_and_GR64_TC -1    GR64_NOREX -1    GR64_TC -1    LOW32_ADDR_ACCESS_with_sub_32bit+GR64_TC -1    GR64_TC+GR64_TCW64 -1    GR8 -1    GR8+GR64_NOREX -1    GR8+GR64_TCW64 -1    GR64_NOREX+GR64_TC -1    GR8+GR64_TC -1    GR16 -1

SU(2):   %XMM0<def> = COPY %vreg2; FR64:%vreg2
  # preds left       : 1
  # succs left       : 1
  # rdefs left       : 0
  Latency            : 0
  Depth              : 4
  Height             : 0
  Predecessors:
   data SU(0): Latency=4 Reg=%vreg2
  Successors:
   ord  SU(4294967295) *: Latency=0
  Pressure Diff      : VR128L -1

Max Pressure: GR8_ABCD_H=1
GR8_ABCD_L=1
VR128L=1
GR32_TC=2
LOW32_ADDR_ACCESS_with_sub_32bit+GR64_NOREX_and_GR64_TCW64=2
GR64_NOREX_and_GR64_TC=2
LOW32_ADDR_ACCESS_with_sub_32bit+GR64_NOREX_and_GR64_TC=2
FR32=1
GR64_NOREX=2
GR64_TCW64=2
LOW32_ADDR_ACCESS_with_sub_32bit+GR64_TCW64=2
GR64_TC=2
LOW32_ADDR_ACCESS_with_sub_32bit+GR64_TC=2
GR64_TC+GR64_TCW64=2
GR8=2
GR8+GR64_NOREX=2
GR8+GR64_TCW64=2
GR64_NOREX+GR64_TC=2
GR8+GR64_TC=2
FR32X=1
GR16=2
Live In: 
Live Out: AH AL
Live Thru: 

BB#0: derived from LLVM BB %entry
  ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
---------------------------------------------------------------------------------------------------------------------------------------------
  %vreg2<def> = MOVSDrm %RIP, 1, %noreg, <cp#0>, %noreg; mem:LD8[ConstantPool] FR64:%vreg2
  %EDI<def,dead> = MOV32ri64 <ga:@_ZSt4cout>, %RDI<imp-def>
  %XMM0<def> = COPY %vreg2; FR64:%vreg2
---------------------------------------------------------------------------------------------------------------------------------------------
  CALL64pcrel32 <ga:@_ZNSo9_M_insertIdEERSoT_>, <regmask %BH %BL %BP %BPL %BX %EBP %EBX %RBP %RBX %R12 %R13 %R14 %R15 %R12B %R13B %R14B %R15B %R12D %R13D %R14D %R15D %R12W %R13W %R14W %R15W>, %RSP<imp-use>, %RDI<imp-use,kill>, %XMM0<imp-use,kill>, %RSP<imp-def>, %RAX<imp-def>
  ADJCALLSTACKUP64 0, 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
  %vreg3<def> = COPY %RAX<kill>; GR64:%vreg3
  ADJCALLSTACKDOWN64 0, 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
  %RDI<def> = COPY %vreg3; GR64:%vreg3
  %ESI<def,dead> = MOV32ri64 <ga:@.str>, %RSI<imp-def>
  %EDX<def,dead> = MOV32ri64 1, %RDX<imp-def>
  CALL64pcrel32 <ga:@_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l>, <regmask %BH %BL %BP %BPL %BX %EBP %EBX %RBP %RBX %R12 %R13 %R14 %R15 %R12B %R13B %R14B %R15B %R12D %R13D %R14D %R15D %R12W %R13W %R14W %R15W>, %RSP<imp-use>, %RDI<imp-use,kill>, %RSI<imp-use,kill>, %RDX<imp-use,kill>, %RSP<imp-def>, %RAX<imp-def,dead>
  ADJCALLSTACKUP64 0, 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
  %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
  RET 0, %EAX<kill>
  
These are the PSets with mismatches in this region.

 R8_ABCD_H
R8_ABCD_L
R32_TC Limit
OW32_ADDR_ACCESS_with_sub_32bit+GR64_NOREX_and_GR64_TCW64

Thanks,

Austin Kerbow