[llvm-dev] Specifying register constraints on instruction definitions

Johnson, Nicholas Paul via llvm-dev llvm-dev at lists.llvm.org
Wed Apr 5 13:02:44 PDT 2017

I see that instruction specifications may include a 'Constraints' attribute which forces the register allocator to choose the same register for two operands.

Is it possible to write constraints such that one operand must be a subregister of another?

Nick Johnson
D. E. Shaw Research

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