[llvm-dev] Scheduler: modelling long register reservations?

[Johnson, Nicholas Paul via llvm-dev]

Hello,

My out-of-tree target features some high latency instructions (let's call them FXLV).  When an FXLV issues, it reserves its destination register and execution continues; if a subsequent instruction attempts to read or write that register, the pipline will stall until the FXLV completes.  I have attempted to encode this constraint in the machine scheduler (excerpt at bottom of email).  This solves half of the problem: the scheduler moves any instruction that reads the FXLV result register to a much later position.

However, this doesn't solve all of the problem.  In particular, the scheduler seems indifferent to an instruction which overwrites the FXLV's result register---including instructions which overwrite only one lane of the vector result.  Am I specifying the scheduling constraints incorrectly?  Can llvm support this kind of constraint?

Thank you,
Nick Johnson
D. E. Shaw Research


// Excerpted from lib/Target/MyTarget/MyTargetSchedule.td:
//
def DesGCv3GenericModel : SchedMachineModel
{
  let IssueWidth = 1;
  let MicroOpBufferSize = 0;

  let CompleteModel = 1;
}
// ...
def FlexU        : ProcResource<64> { let BufferSize = 1; }
def : WriteRes<IIFlexRead,   [FlexU]>          { let Latency = 25; let ResourceCycles = [25]; }
class SchedFlexRead    : Sched< [IIFlexRead] >; // I apply this to the definition of FXLV instruction
// ...