[llvm-dev] Reg units for unaddressable register parts?

[Krzysztof Parzyszek via llvm-dev]

On 9/29/2016 7:48 PM, Quentin Colombet wrote:
> The reason I am asking is because I believe it may already be possible
> to add unaddressable register units by hand.
> One would need to create additional subregs in their td file to fill the
> holes, then mark all the registers mapping to those subregs as
> unallocatable.
>
> E.g.,
> let SubRegIndices = [sub_16bit] in {
> def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
>
> —>
> let SubRegIndices = [*dummysubIdx_16bit,* sub_16bit] in {
> def EAX : X86Reg<"eax", 0, [*ADummyXH*, AX]>, DwarfRegNum<[-2, 0, 0]>;
> […]
> def DummyRegClass : RegisterClass[…]/*list all dummy regs*/ {
> isAllocatable = 0;
> }
>
> In other words, you may be able to explore if that would solve your
> problem or if we have to come up with something smarter.


I think this would solve it!

-Krzysztof