[llvm-dev] Receiving LLVM Error in Custom Backend
Ryan Taylor via llvm-dev
llvm-dev at lists.llvm.org
Fri Sep 9 10:11:03 PDT 2016
The DAG pattern is not represented in table-gen, that's what the error is
telling you. During the DAG selection phase, the DAG pattern is not
represented anywhere in table-gen so it's unable to move further in the
flow... and produces an error.
I'm not sure what you're trying to do exactly but try to represent this
pattern in table-gen. If the arch doesn't support the pattern, then you
might have to something with it in the DAG.
You should be able to see this if you do something like: llc
-view-isel-dags yourfile.ll (and you have vizgraph, etc.. setup). This
will show the DAG just before ISel phase.
On Fri, Sep 9, 2016 at 12:28 PM, Mush Yien <yienmush at gmail.com> wrote:
> Hi Ryan,
> I am trying, but am not sure I am doing it right. I am having a problem
> understanding the error tbh, is it complaining that the load instruction is
> not being matched? or that i16 is not defined? I can't seem to get my head
> around the specific error :S
> On Wed, Sep 7, 2016 at 6:39 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>> R u trying to match this pattern in table gen?
>> On Sep 7, 2016 12:12, "Mush Yien via llvm-dev" <llvm-dev at lists.llvm.org>
>>> I am receiving an LLVM Error from a custom 16-bit backend I am
>>> creating. I am having trouble understanding the error/problem and how to
>>> go about solving it. The error is:
>>> LLVM ERROR: Cannot select: t29: i32,ch = load<LD2[%x.addr], anyext from
>>> i16> t14, FrameIndex:i16<0>, undef:i16
>>> t7: i16 = FrameIndex<0>
>>> t9: i16 = undef
>>> In function: mul_add
>>> Can anyone provide any pointers as to what the problem is and potential
>>> places I should look to fix it?
>>> Thanks and best regards,
>>> LLVM Developers mailing list
>>> llvm-dev at lists.llvm.org
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