[llvm-dev] Generate Register Indirect mode instruction

[Alex Bradley via llvm-dev]

> You probably want to look at the x86 backend; it has a lot of
instructions which involve both computation and memory.  Take the following
IR, a variant of your example:
>
> define void @foo(i32 *%a, i32 *%b, i32 *%c) {
> entry:
>   %0 = load i32, i32* %a, align 4
>   %1 = load i32, i32* %b, align 4
>
>   %add = add nsw i32 %1, %0
>   store i32 %add, i32* %c, align 4
>   ret void
> }
>
> The x86 backend generates the following:
>
>         movl    (%rsi), %eax
>         addl    (%rdi), %eax
>         movl    %eax, (%rdx)
>         retq
>
> Note in particular the memory operand embedded into the addition.
>
> The way the LLVM x86 backend models this is just to pattern match it
during instruction selection: it matches a pattern like  (add r, (load
addr)) to a single instruction.

Thanks Eli. I will have a look into it. However, the above x86 code loads
the content of the memory location into eax register and adds that register
with another memory location.

My target loads the address of the memory locations in the registers for
both the operands and then uses add operation on the registers in an
indirect way. How do I specify that in .td files so that it matches in
ISelDAGToDAG select() function? Any small example?

Thanks for example code :)

Regards,
Alex
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