[llvm-dev] [RFC] Supporting ARM's SVE in LLVM

[Renato Golin via llvm-dev]

On 29 November 2016 at 21:33, Chandler Carruth <chandlerc at gmail.com> wrote:
> Ok, I'm still catching up on this thread, but I think starting to review
> patches is going to make it substantially harder to have a productive
> conversation. We haven't yet really gotten to any kind of consensus around
> the design, and until then I think it would be very helpful to keep
> discussion focused on the high-level threads on llvm-dev rather than
> fragmenting it into the commits list threads for the patches. I'm happy to
> have patches as FYI examples, but they shouldn't be the focus of the
> discussion.

For now, I'm treating the reviews as a concrete example of
implementation, not as a normal approved-merge series. Just like new
back-ends, this will take a lot more than just a few people to look at
it and "approve".

So, if you're worried that high-level decisions will be taken on those
(and subsequent) reviews by approving them, don't be.

Also, any design discussion *will* need to be in the list, not on the reviews.

If I pick up anything on the reviews that wasn't discussed on the
list, I'll make sure to mention it on the reviews (ie. "please, spawn
a new RFC").


> Also, up the thread and even in this email there is significant talk about a
> substantial change of design based on feedback from the dev meeting. But
> there are over 40 emails already here and I've not found an actual concise
> high level overview of the *new* design.

The refactoring, AFAICS, was just about vscale and stepvector, both of
which were mentioned on Graham's reply to my questions (the fifth
email on my list).

Everything else is still "working around the concept" of scalable
vectors, IR representation, shuffle/insert/extract semantics, etc.


> I suspect it would be helpful to start a fresh RFC thread with a *concise*
> description of the new design so that folks can skip ahead and more
> productively join that discussion.

There were more substantial comments along the thread than those.
We're not at the point where a new RFC would be beneficial, I think.

The thread has calmed down a bit, take your time to read. I just added
you to the reviews as a FYI, not for us to take any decision right
now. We still need to understand how scalable vectors will look like
in RISC-V, so we only change the IR if we really have to and only
once. But for that, we need context, which we don't have yet.

The bottom line is: we can't approve the high-leve IR changes until
we're sure it encompass all new syntax we need and doesn't break any
old syntax we already have. Unfortunately, for now, without more
information on SVE and RISC-V's scalable extension, everything is
mostly ethereal. But it's a conversation worth having.

cheers,
--renato