[llvm-dev] [RFC] Supporting ARM's SVE in LLVM

[Renato Golin via llvm-dev]

On 28 November 2016 at 14:36, Paul Walker <Paul.Walker at arm.com> wrote:
> SVE has a similar instruction that returns the current vector length (rdvl).  The reason you don’t see it in our example loop’s instruction output is because in that example we are able to use “incw x2” that increments x2 by the number of i32s a vector can hold.
>
> None of our proposals are syntactic sugar with all having relevance to directing efficient code generation.

Ok, makes sense. Your proposal is also not affected by using "vscale"
or %vscale on the induction variable.

cheers,
--renato