[llvm-dev] [RFC] Supporting ARM's SVE in LLVM

[Paul Walker via llvm-dev]

>>(1)     %index.next = add nuw nsw i64 %index, mul (i64 vscale, i64 4)
>>(2)     %index.next = add nuw nsw i64 %index, mul (i64 vscale, i64 16)
>>
>>The runtime part of the scalable vector lengths remains the same with the second loop processing 4x the number of elements per iteration.

>Right, but this is a "constant", and LLVM would be forgiven by asking
>the "size" of it. With that proposal, there's no way to know if that's
>a <16 x i8> or <16 x i32>.
>
>The vectorizer concerns itself mostly with number of elements, not raw
>sizes, but these types will survive the whole process, especially if
>they come from intrinsics.

What is the relevance of the vector’s element type.  The induction variable update is purely in terms of elements, it doesn’t care about its type. If you need to reference the vector length in bytes you would simply multiply it by the size of vector’s element type just as we do for non-scalable vectors.

Paul!!!