[llvm-dev] [RFC] Supporting ARM's SVE in LLVM

Renato Golin via llvm-dev llvm-dev at lists.llvm.org
Sun Nov 27 08:52:42 PST 2016

On 27 November 2016 at 16:44, Amara Emerson <amara.emerson at gmail.com> wrote:
> Libraries do not require the vector length to be encoded inside them,
> so there is no restriction here. You don't pick a VL for them, the
> point of vector length agnosticism is that the code generated runs
> across ALL vector lengths. However, once your process starts then the
> VL can be assumed to be constant, whatever it is. You could still
> theoretically have two different processes using the same shared
> libraries running with different VLs.

I see. That would only work well if the arguments are passed directly
via SVE vectors. Encoding that in a soft-float variant would be

But also, it would require one to pass the predicate, as it's possible
that the original vectors are restricted. This also fits nicely with
the data/predicate pairs that are always required for SVE vectors.

A simple way would be to mandate z0/p0, z1/p1 to be paired for PCS
purposes. Interesting...


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