[llvm-dev] [RFC] Supporting ARM's SVE in LLVM
Renato Golin via llvm-dev
llvm-dev at lists.llvm.org
Sun Nov 27 08:25:33 PST 2016
On 27 November 2016 at 16:10, Amara Emerson <amara.emerson at gmail.com> wrote:
> No. Let's make one thing clear now: we don't expect the VL to be
> changed on the fly, once the process is started it's fixed. Otherwise
> things like stack frames with SVE objects will be invalid.
This then forbids different lengths on shared objects, which in turn
forces all objects in the same OS to have the same length. Still a
kernel option (like VMA or page tables sizes), but not on a
Like ARM's ABI, it only makes sense to go that far on public interfaces.
Given how distros are conservative on their deployments, can force
"normal" people using SVE (ie. not super-computers) to either accept
the lowest denominator or to optimise local code better.
Or distros will base that on the hardware default value (reported via
kernel interface) and the deployment will be per-process... or there's
will be multilib.
In any case, SVE is pretty cool, but deployment is likely to be *very*
complicated. Nothing we haven't seen with AArch64, or worse, on ARM,
> 1. The vectorizer will have to deal with loop carried dependences as
> normal, if it doesn't have a guarantee about the VL then it has to
> either avoid vectorizing some loops, or it can cap the effective
> vectorization factor by restricting the loop predicate to a safe
This should be easily done via the predicate register.
> 2. Yes the cost model is more complicated, but it's not necessarily
> the case that we assume the smallest VL. We can cross that bridge when
> we get to it though.
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