[llvm-dev] Bad ARM instruction "sub.w sp, r7, #8" allowed by Clang

[Tim Northover via llvm-dev]

Hi Gael,

On 9 November 2016 at 01:53, Gaël Jobin via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Given that it is the first time I mess with the ARM backend, what do
> you think of this fix?

The analysis seems spot on, thanks for taking the time to look into
this and work on a solution.

We do have a better register class: "rGPR" only excludes SP and PC
(tGPR is just the Thumb1 registers r0-r7).

> Did I miss something? As the fix is not complete
> (it does not support the "SUB (SP minus register)"), any idea how to
> implement this special instruction ?

They'll probably have to be separate instructions, "t2SUBspi" or
something where Rn can only be SP. Analogous to tSUBspi that already
exists. TableGen can't easily encode Rd != SP unless Rn == SP.

Let me know if anything's still unclear.

Tim.