[llvm-dev] Prioritizing an SDNode for scheduling
Alex Susu via llvm-dev
llvm-dev at lists.llvm.org
Wed Nov 9 04:05:25 PST 2016
I have tried hard, but in the end I chose a different solution: I change the order of
machine instructions by using the ASM writer classes such as [Target]AsmPrinter.cpp. There
the code is already scheduled, in a list of instructions and it's very easy to move the
instructions in the list.
(Following Ehsan's advice I looked at
http://llvm.org/docs/doxygen/html/classllvm_1_1GenericScheduler.html for example, but I
did not get any idea.)
On 10/21/2016 5:32 PM, Ehsan Amiri wrote:
> I probably misunderstood the question. You probably want to do this in SelectionDAG.
> On Fri, Oct 21, 2016 at 10:29 AM, Ehsan Amiri <ehsanamiri at gmail.com
> <mailto:ehsanamiri at gmail.com>> wrote:
> You can do this by changing instruction scheduling heuristics. I think the more
> important question is if this correct always for all platforms.
> I don't know which scheduler you use. We use GenericScheduler and PostGenericScheduler
> before and after RA. These classes have a ::tryCandidate method which compares two
> instructions that can be legally scheduled and decide which of the two should be
> scheduled. Currently these method are target independent.
> The correctness question still remains open for me.
> On Thu, Oct 20, 2016 at 8:08 PM, Alex Susu via llvm-dev <llvm-dev at lists.llvm.org
> <mailto:llvm-dev at lists.llvm.org>> wrote:
> Is there a way to specify in the back end an (ISD::INLINEASM) SDNode to be
> scheduled first under all circumstances? I need to specify something like node
> priority to schedule the node before all other nodes in the SelectionDAG of the
> basic block.
> (Using chain or glue edges in order to make a node first is not a good idea,
> since I am doing this at instruction selection time, on individual nodes.)
> Thank you,
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
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