[llvm-dev] MC PowerPC 32 bit vs. 64 bit
Keve via llvm-dev
llvm-dev at lists.llvm.org
Sun Nov 6 11:24:22 PST 2016
over the past days I have been proofing a concept involving LLVM MC on
the PowerPC target. The 32 bit part went quite ok, but i am puzzled with
the results I get using the 64 bit target.
When disassembling in 64bit some instructions refer to GPRs in PPC::R0
to PPC::R31, some refer to PPC::X0 to PPC::X31.
I understand that the registers are modeled with Rx referring to the
32bit parts and Xx referring to the 64bit parts, but the way it looks to
me right now is that you only get the 64bit registers if the opcode is
available exclusively in 64bit mode.
I have seen that many instructions have been duplicated to support 32
bit registers and 64 bit register, e.g. oris vs. oris8, but the
disassembler does not pick the 64 bit variant.
PPCGenDisassemblerTables.inc does not have anything about oris8, only oris.
As a user of the Disassembler I would expect it to return me the 64bit
instruction referencing the 64bit registers if I ask it to disassemble a
Is this intended behavior or am I just missing some bit somewhere?
Thank you very much in advance for clarifying this.
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