[llvm-dev] Better way to define instructions using multiclasses?

Markus Weinhardt via llvm-dev llvm-dev at lists.llvm.org
Sun May 29 08:55:05 PDT 2016

Hello everyone,

I'm still new to llvm and therefore wonder if there's a shorter way for
the following situation, see attached td-file:

My processor has a FPU where both operands can read from a register or
from memory, and the result can be stored in a register or in memory. I
defined two cases (output to register _r and to memory _m) in a
multiclass. But I had to repeat similar code four times for the four
possible operand combinations.

I'd like to define the two possibilities for each operand independently,
i.e. e.g. for Ty:$srca and (load LoadRegs:$ptra), and automatically
generate all combinations. Is this possible?

Thanks for any advice!

Best regards,

Prof. Dr.-Ing. Markus Weinhardt -  Hochschule Osnabrück
Visiting Researcher at www.inesc-id.pt -ESDA, Lisbon/PT
mweinhardt at computer.org  -  Tel.nr. +49-(0)541-969 3445
Postf. 1940, 49009 Osnabrück (Artilleriestr. 46, SB223)
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