[llvm-dev] Handling post-inc users in LSR

via llvm-dev llvm-dev at lists.llvm.org
Fri May 27 14:50:53 PDT 2016


For a very simple loop where all IV users are post-inc users, I observed 
redundant add instructions in AArch64.

 From LSR debug, I can see initial formula for icmp is the one that 
transformed to a post-inc form in OptimizeLoopTermCond() and later 
expanded in post-inc mode.  Based on the observation that the icmp is 
already a post-inc user, I hacked LSR to prevent the icmp from being 
transformed to post-inc form  in OptimizeLoopTermCond() before the 
initial formulae are determined. Luckily, I was able to remove the 
redundant  add  instruction with this hack, but I really doubt if it 
make sense to prevent a loop terminating condition from being changed to 
postinc form when it's already a post-inc user.

# Input IR :

define void @foo(i32 %n, i32* %P) {
   %cmp7 = icmp sgt i32 %n, 1
   br i1 %cmp7, label %for.body.preheader, label %for.end

for.body.preheader:                               ; preds = %entry
   %n_sext = sext i32 %n to i64
   br label %for.body

   %K.in = phi i64 [ %n_sext, %for.body.preheader ], [ %K, %for.body ]
   %K = add i64 %K.in, 1

   %StoredAddr = getelementptr i32, i32* %P, i64 %K
   %StoredValue = trunc i64 %K to i32
   store volatile i32 %StoredValue, i32* %StoredAddr
   %cmp = icmp sgt i64 %K, 1
   br i1 %cmp, label %for.body, label %for.end

   ret void

# Output in AArch64 where you can see redundant add instructions for 
stored value, store address, and in cmp :

// BB#0:
	cmp		w0, #2
	b.lt	.LBB0_3
// BB#1:
	sxtw	x9, w0
	add	w8, w0, #1
	add	x10, x1, x9, lsl #2
	add	x9, x9, #1
	str	w8, [x10, #4]
	add	w8, w8, #1
	cmp		x9, #1
	b.gt	.LBB0_2

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