[llvm-dev] Liveness of AL, AH and AX in x86 backend

mats petersson via llvm-dev llvm-dev at lists.llvm.org
Tue May 24 10:03:41 PDT 2016

On several variants of x86 processors, mixing `ah`, `al` and `ax` as
source/destination in the same dependency chain will have some penalties,
so for THOSE processors, there is a benefit to NOT use `al` and `ah` to
reflect parts of `ax` - I believe this is caused by the fact that the
processor doesn't ACTUALLY see these as parts of a bigger register
internally, and will execute two independent dependency chains, UNTIL you
start using `ax` as one register. At this point, the processor has to make
sure both of dependency chains for `al` and `ah` have been complete, and
that the merged value is available in `ax`. If the processor uses `cl` and
`al`, this sort of problem is avoided.

<<Quote from Intel Optimisation guide, page 3-44

A partial register stall happens when an instruction refers to a register,
portions of
which were previously modified by other instructions. For example, partial
stalls occurs with a read to AX while previous instructions stored AL and
AH, or a read
to EAX while previous in
struction modified AX.
The delay of a partial register stall is small in processors based on Intel
Core and
NetBurst microarchitectures, and in Pentium M processor (with CPUID
family 6, model 13), Intel Core Solo,
and Intel Core Duo processors. Pentium M
processors (CPUID signature with family 6,
model 9) and the P6 family incur a large
<<Enq quote>>

So for compact code, yes, it's probably an advantage. For SOME processors
in the x86 range, not so good for performance.

Whether LLVM has the information as to WHICH processor models have such
penalties (or better yet, can determine the amount of time lost for this
sort of operation), I'm not sure. It's obviously something that CAN be
programmed into a compiler, it's just a matter of understanding the effort
vs. reward factor for this particular type of optimisation, compared to
other things that could be done to improve the quality of the code


On 24 May 2016 at 17:09, Smith, Kevin B via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Try using x86 mode rather than Intel64 mode.  I have definitely gotten it
> to use both ah and al in 32 bit x86 code generation.
> In particular, I have seen that in loops for both the spec2000 and
> spec2006 versions of bzip.  It can happen, but it does only rarely.
> Kevin Smith
> >-----Original Message-----
> >From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of
> >Krzysztof Parzyszek via llvm-dev
> >Sent: Tuesday, May 24, 2016 8:04 AM
> >To: LLVM Dev <llvm-dev at lists.llvm.org>
> >Subject: [llvm-dev] Liveness of AL, AH and AX in x86 backend
> >
> >I'm trying to see how the x86 backend deals with the relationship
> >between AL, AH and AX, but I can't get it to generate any code that
> >would expose an interesting scenario.
> >
> >For example, I wrote this piece:
> >
> >typedef struct {
> >   char x, y;
> >} struct_t;
> >
> >struct_t z;
> >
> >struct_t foo(char *p) {
> >   struct_t s;
> >   s.x = *p++;
> >   s.y = *p;
> >   z = s;
> >   s.x++;
> >   return s;
> >}
> >
> >But the output at -O2 is
> >
> >foo:                                    # @foo
> >         .cfi_startproc
> ># BB#0:                                 # %entry
> >         movb    (%rdi), %al
> >         movzbl  1(%rdi), %ecx
> >         movb    %al, z(%rip)
> >         movb    %cl, z+1(%rip)
> >         incb    %al
> >         shll    $8, %ecx
> >         movzbl  %al, %eax
> >         orl     %ecx, %eax
> >         retq
> >
> >
> >I was hoping it would do something along the lines of
> >
> >   movb (%rdi), %al
> >   movb 1(%rdi), %ah
> >   movh %ax, z(%rip)
> >   incb %al
> >   retq
> >
> >
> >Why is the x86 backend not getting this code?  Does it know that AH:AL =
> >AX?
> >
> >-Krzysztof
> >
> >
> >
> >--
> >Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> >hosted by The Linux Foundation
> >_______________________________________________
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> >llvm-dev at lists.llvm.org
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