[llvm-dev] Struggling to define a simple instruction

Rail Shafigulin via llvm-dev llvm-dev at lists.llvm.org
Mon May 16 14:56:25 PDT 2016

I'm trying to figure out how I can define and make LLVM target a simple

The instruction is very simple, it adds all of the elements of the vector
register. Lets' call it sum_reduce.

Defining a vector add was simple. All I had to do is to simply change the
register type used by a regular add instruction and that was it. However
I'm really struggling to define this new instruction.

Initially I thought that I would replace a chain of 3 adds with
insert_element instructions, but that defeats the purpose of sum_reduce,
since it would mean that I have to insert operators 4 times into a vector
register and then add everything. This turns it into more instructions than
the original chain of 3 adds.

I've also looked at X86 HADD instructions but also have difficulty
understanding how to implement something similar to it in my target.
I've annoyed enough people on the LLVM IRC channel. And they have been
really helpful, unfortunately I feel that if I ask more they'll stop
answering completely :D

At this point I wouldn't mind some handholding.  I can provide more code if

Any help on the issue is really appreciated.

Rail Shafigulin
Software Engineer
Esencia Technologies
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