[llvm-dev] Atomic LL/SC loops in llvm

JF Bastien via llvm-dev llvm-dev at lists.llvm.org
Tue May 10 14:04:54 PDT 2016

Thanks for the writeup, that is indeed pretty ugly. Simple asm(:::"memory")
isn't sufficient either, since the regalloc can decode to spill :-(

On Tue, May 10, 2016 at 12:22 PM, James Knight via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Unfortunately, neither ARM nor PPC appear to precisely document the
> architectural constraints under which forward progress must be guaranteed
> by the implementation. They certainly have the same underlying
> implementation issues that give rise to the above rules -- that much seems
> documented -- they just don't appear to make explicit guarantees on how you
> can guarantee success. ARM does "recommend" that LL/SC loops fit within 128
> bytes, though.

For ARMv7 from the ARM ARM:

A Load-Exclusive instruction tags a small block of memory for exclusive
access. The size of the tagged block is IMPLEMENTATION DEFINED, see Tagging
and the size of the tagged memory block on page A3-121. A Store-Exclusive
instruction to the same address clears the tag.


The value of a in this assignment is IMPLEMENTATION DEFINED, between a
minimum value of 3 and a maximum value of 11. For example, in an
implementation where a is 4, a successful LDREX of address 0x000341B4 gives
a tag value of bits[31:4] of the address, giving 0x000341B. This means that
the four words of memory from 0x000341B0 to 0x000341BF are tagged for
exclusive access.
The size of the tagged memory block is called the Exclusives Reservation
Granule. The Exclusives Reservation Granule is IMPLEMENTATION DEFINED in
the range 2-512 words:
• 2 words in an implementation where a is 3

• 512 words in an implementation where a is 11
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