[llvm-dev] Illegal operand for the record

[Rail Shafigulin via llvm-dev]

I'm trying to define new set of instructions, however I'm getting an error:

error:Illegal operand for the 'VADDvg' instruction!

I know the error is coming from
https://github.com/llvm-mirror/llvm/blob/eab2869a64182bf66a53fac3c73458f29a3c43e5/utils/TableGen/CodeGenInstruction.cpp#L67

but I can't figure out what it means.

Below is the code that is causing the error. Would anyone care to help out?
Many thanks in advance.

class VALU0vv<bits<8> subOp, string asmstr, SDNode OpNode>
  : InstFRR<subOp, (outs VR:$rD), (ins VR:$rA, VR:$rB),
           !strconcat(asmstr, "\t$rD, $rA, $rB"),
           [(set VR:$rD, (OpNode VR:$rA, VR:$rB))]> {
  bits<5> rD;
  bits<5> rA;
  bits<5> rB;

  let Inst{25-21} = rD;
  let Inst{20-16} = rA;
  let Inst{15-11} = rB;
}

class VALU0vg<bits<8> subOp, string asmstr, SDNode OpNode>
  : InstFRR<subOp, (outs VR:$rD), (ins VR:$rA, (i32 GPR:$rB)),
           !strconcat(asmstr, "\t$rD, $rA, $rB"),
           [(set VR:$rD, (OpNode VR:$rA, (i32 GPR:$rB)))]> {
  bits<5> rD;
  bits<5> rA;
  bits<5> rB;

  let Inst{25-21} = rD;
  let Inst{20-16} = rA;
  let Inst{15-11} = rB;
}

multiclass VALU1<bits<8> subOp1, bits<8> subOp2, string asmstr, SDNode
OpNode> {
  def vv : VALU0vv<subOp1, asmstr, OpNode>;
  def vg : VALU0vg<subOp2, asmstr, OpNode>;
}

let Itinerary = l_add in
  defm VADD : VALU1<0x07, 0x08, "v.add", add>;


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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