[llvm-dev] tricky constraints in backend

[Konstantin Vladimirov via llvm-dev]

Hi,

I am working on custom LLVM 3.7 backend, already having GCC backend.
In GCC backend there are perfectly legal address constraints like
"A32", which are widely used in inline assembler.

I am trying to support those in LLVM, but there is a problem in
llvm::InlineAsm::ConstraintInfo::Parse function.

it tries to understand A32 as two separate constraints: one-letter "A"
and numeric "32", latter, of course, fails (numeric 32 constraint
means "32-nd parameter", and there are no 32 parameters).

It is called very early, from llvm::InlineAsm::InlineAsm ctor, where
assert fails for this reason, so even llvm IR is not emitted.

Is there a way to support multi-letter target-specific constraints
with trailing digits?

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WIth best regards, Konstantin