[llvm-dev] Enable / Disable a processor feature

[Rail Shafigulin via llvm-dev]

Thanks for the reply. The issue was that I did look at an existing target,
but wasn't able to figure it out, at least initially. I figured it right
now (with llc use -mattr=+feature1,-feature2,+feature3 to enable feature1,
disable feature2 and enable feature3 respectively), but still have
questions. For example, clang has this
-target-feature=+feature1,-feature2,+feature3, but for some reason it
didn't work for my target. I'm wondering why it didn't. I would really like
to know why it didn't work. I can post more code if you are interested in
helping out.


On Mon, Mar 7, 2016 at 1:34 PM, Eric Christopher <echristo at gmail.com> wrote:

> The easiest way here is to take a look at an existing target, say x86, and
> do what it does :)
>
> For specific guidance within x86, take a look at how -msse3 works.
>
> -eric
>
> On Fri, Mar 4, 2016 at 5:25 PM Rail Shafigulin via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> I'm trying to enable/disable a target feature through clang.
>>
>> Here is how my target looks like
>>
>> // Esencia subtarget features
>>
>> //===----------------------------------------------------------------------===//
>> def FeatureMul   : SubtargetFeature<"mul", "HasMul", "true",
>>                                    "Enable hardware multiplier">;
>> def FeatureDiv   : SubtargetFeature<"div", "HasDiv", "true",
>>                                    "Enable hardware divider">;
>> def FeatureCmov  : SubtargetFeature<"cmov", "HasCmov", "true",
>>                                     "Enable conditional move
>> instruction">;
>> def FeatureAddc  : SubtargetFeature<"addc", "HasAddc", "true",
>>                                     "Enable add with carry instruction">;
>>
>>
>> //===----------------------------------------------------------------------===//
>> // Esencia processors supported.
>>
>> //===----------------------------------------------------------------------===//
>> class Proc<string Name, SchedMachineModel Model,
>>            list<SubtargetFeature> Features>
>>  : ProcessorModel<Name, Model, Features>;
>>
>> def : Proc<"esencia", EsenciaModel, [FeatureMul,
>>                                      FeatureDiv,
>>                                      FeatureCmov,
>>                                      FeatureAddc
>>                                     ]>;
>>
>> This is what I have in EsenciaTargetInfo::setFeatureEnabled(...) in
>> clang/lib/Basic/Targets.cpp
>>
>>   virtual void setFeatureEnabled(llvm::StringMap<bool> &Features,
>>                                  StringRef Name,
>>                                  bool Enabled) const {
>>     if (Name == "mul" ||
>>         Name == "div" ||
>>         Name == "cmov" ||
>>         Name == "addc") {
>>       Features[Name] = Enabled;
>>     }
>>   }
>>
>> Is there a way to enable/disable a given feature through clang? Any flags
>> I need to pass?
>>
>> Any help is appreciated.
>>
>> --
>> Rail Shafigulin
>> Software Engineer
>> Esencia Technologies
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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