[llvm-dev] Early CSE clobbering llvm.assume

Lawrence, Peter via llvm-dev llvm-dev at lists.llvm.org
Tue Jun 14 10:36:14 PDT 2016

              What am I missing in the following chain of logic:

As far as constant-prop, value-prop, range-prop, and general property-propagation,

1. the compiler/optimizer *has* to get it right for if-then-else and while-do or else we should all start over ☺

2. “assert” takes advantage of this by being translated into if-then logic early on in the compilation

3. “assume” should also take advantage of this the same way. (generate a call to “pseudoabort” which
At some late stage gets deleted)

Sanjoy’s argument is faulty, if it were true we would also find our handling of “assert” to be unacceptable
but this is not the case, no one is arguing that we need to re-design “assert”.

And any argument you can make about needing to handle “assume” conditions in some special way can be
Turned around and applied to “if-then” conditions, but again no one is arguing that we need to re-design “if-then”
Information propagation.


From: Daniel Berlin [mailto:dberlin at dberlin.org]
Sent: Saturday, June 11, 2016 6:17 PM
To: Sanjoy Das <sanjoy at playingwithpointers.com>; Sean Silva <chisophugis at gmail.com>
Cc: Lawrence, Peter <c_plawre at qca.qualcomm.com>; llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] Early CSE clobbering llvm.assume

What he said :)
It also, representationally, has a related  issue  our current assume does in terms of figuring out the set of assumptions applied.  Given an instruction, in extended SSA, because " assume" produces a value used by things, it's trivial to find the chain of assumptions you can use for it.  In a straight control flow representation, it requires finding which side of the branch you are on all the way up the control dependence tree

On Sat, Jun 11, 2016, 6:07 PM Sanjoy Das via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:
On Sat, Jun 11, 2016 at 5:47 PM, Sean Silva via llvm-dev
<llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:
> Perhaps a naive question then is: why don't we represent assume as `if
> (!cond) unreachable; else <the rest of the code>`?

As I understand it, in theory this is fine, but in practice it may end
up breaking optimizations.  For instance, today we can hoist loads
across calls to assume, but it may not be obviously safe if you have
the branch-to-unreachable representation.   The control flow
representation may also bloat compile time / memory usage due to more
basic blocks.

-- Sanjoy
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