[llvm-dev] [Proposal][RFC] Cache aware Loop Cost Analysis

Hal Finkel via llvm-dev llvm-dev at lists.llvm.org
Wed Jun 8 09:50:07 PDT 2016

----- Original Message -----

> From: "Vikram TV via llvm-dev" <llvm-dev at lists.llvm.org>
> To: "DEV" <llvm-dev at lists.llvm.org>
> Sent: Wednesday, June 8, 2016 2:58:17 AM
> Subject: [llvm-dev] [Proposal][RFC] Cache aware Loop Cost Analysis

> Hi,

> This is a proposal about implementing an analysis that calculates
> loop cost based on cache data. The primary motivation for
> implementing this is to write profitability measures for cache
> related optimizations like interchange, fusion, fission,
> pre-fetching and others.

> I have implemented a prototypical version at
> http://reviews.llvm.org/D21124 .
I quick comment on your pass: You'll also want to add the ability to get the loop trip count from profiling information from BFI when available (by dividing the loop header frequency by the loop predecessor-block frequencies). 

> The patch basically creates groups of references that would lie in
> the same cache line. Each group is then analysed with respect to
> innermost loops considering cache lines. Penalty for the reference
> is:
> a. 1, if the reference is invariant with the innermost loop,
> b. TripCount for non-unit stride access,
> c. TripCount / CacheLineSize for a unit-stride access.
> Loop Cost is then calculated as the sum of the reference penalties
> times the product of the loop bounds of the outer loops. This loop
> cost can then be used as a profitability measure for cache reuse
> related optimizations. This is just a brief description; please
> refer to [1] for more details.
This sounds like the right approach, and is certainly something we need. One question is how the various transformations you name above (loop fusion, interchange, etc.) will use this analysis to evaluate the effect of the transformation they are considering performing. Specifically, they likely need to do this without actually rewriting the IR (speculatively). 

> A primary drawback in the above patch is the static use of Cache Line
> Size. I wish to get this data from tblgen/TTI and I am happy to
> submit patches on it.
Yes, this sounds like the right direction. The targets obviously need to provide this information. 

> Finally, if the community is interested in the above work, I have the
> following work-plan:
> a. Update loop cost patch to a consistent, commit-able state.
> b. Add cache data information to tblgen/TTI.
> c. Rewrite Loop Interchange profitability to start using Loop Cost.

This does not affect loop interchange directly, but one thing we need to also consider is the number of prefetching streams supported by the hardware prefetcher on various platforms. This is generally, per thread, some number around 5 to 10. Splitting loops requiring more streams than supported, and preventing fusion from requiring more streams than supported, is also an important cost metric. Of course, so is ILP and other factors. 


> Please share your valuable thoughts.

> Thank you.

> References:
> [1] [Carr-McKinley-Tseng]
> http://www.cs.utexas.edu/users/mckinley/papers/asplos-1994.pdf

> --

> Good time...
> Vikram TV
> CompilerTree Technologies
> Mysore, Karnataka, INDIA
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Hal Finkel 
Assistant Computational Scientist 
Leadership Computing Facility 
Argonne National Laboratory 
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