[llvm-dev] Vector SETCC fails at instruction selection

[Alex Susu via llvm-dev]

   Hello.
     I want to implement vector comparison in my SIMD processor back end.

     To test this I try to compile the following LLVM program:
       define i1 @foo(i64* %A, i64* %B, i1* %C, i64 %N) #0 {
         entry:
           %0 = getelementptr inbounds i64, i64* %A, i64 0
           %1 = bitcast i64* %0 to <8 x i64>*
           %wide.load = load <8 x i64>, <8 x i64>* %1, align 4
           %2 = getelementptr inbounds i64, i64* %B, i64 0
           %3 = bitcast i64* %2 to <8 x i64>*
           %wide.load17 = load <8 x i64>, <8 x i64>* %3, align 4
           %4 = icmp eq <8 x i64> %wide.load17, %wide.load
           %5 = getelementptr inbounds i1, i1* %C, i64 0
           %6 = bitcast i1* %5 to <8 x i1>*
           store <8 x i1> %4, <8 x i1>* %6, align 4
           %res = load i1, i1* %C, align 4
           ret i1 %res
       }
     But, I get with llc the following error when compiling the LLVM program:
	Legally typed node: t18: v8i64,ch = load<LD64[%3](align=4)> t0, t4, undef:i64
	Promote integer result: t20: v8i1 = setcc t18, t17, seteq:ch
         llc: /llvm38Nov2016/llvm/lib/CodeGen/TargetLoweringBase.cpp:1399: virtual 
llvm::EVT llvm::TargetLoweringBase::getSetCCResultType(const llvm::DataLayout&, 
llvm::LLVMContext&, llvm::EVT) const: Assertion `!VT.isVector() && "No default SetCC type 
for vectors!"' failed.
     (I can provide a complete -debug output of llc, or I guess even the back end source 
code.)
     (Another thread on llvm-dev reported this error, but no solution was provided: 
https://groups.google.com/forum/#!msg/llvm-dev/443pKsFxQr0/7Qaq3oxBBwAJ .)

     Just to give more details about my implementation of vector SETCC in the back end: as 
usual, I got inspired from the Mips LLVM back end - the MSA SIMD subset. From 
lib/Target/Mips/MipsMSAInstrInfo.td I copied most definitions and classes containing the 
"vset" string in them, and also JUST ONE vsplat record:
     def vseteq_v8i64  : vsetcc_type<v8i64, SETEQ>;
     def vsetle_v8i64  : vsetcc_type<v8i64, SETLE>;
     ...
     def vsplati16 : PatFrag<(ops node:$e0),
                         (v8i16 (build_vector node:$e0, node:$e0,
                                              node:$e0, node:$e0,
                                              node:$e0, node:$e0,
                                              node:$e0, node:$e0))>;

     Also, I wrote in MyConnexISelLowering.cpp:
       SDValue ConnexTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
         ...
         case ISD::EXTRACT_VECTOR_ELT:
           // From [LLVM]/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
           return LowerEXTRACT_VECTOR_ELT(Op, DAG);
         ...
       }

       SDValue ConnexTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
                                                     SelectionDAG &DAG) const {

        return SDValue();
       }


     Could you please tell me if you have any idea with what might be wrong?


   Thank you,
     Alex