[llvm-dev] TableGen change in LLVM 3.9 allows only prefix ASM instruction notation

Alex Susu via llvm-dev llvm-dev at lists.llvm.org
Sun Jul 17 02:14:07 PDT 2016

     Tim, thanks for pointing me out to https://github.com/llvm-mirror/llvm/commit/5ef1349 .
     I followed the example there and:
       - left utils/TableGen/AsmMatcherEmitter.cpp unchanged (no more commenting of the 
lines I said I did comment in the previous email)
       - following Hexagon.td I added in my MyTarget.td file:
         def MyTargetAsmParser : AsmParser {
           bit HasMnemonicFirst = 0;
         let AssemblyParsers = [MyTargetAsmParser];

      By doing these steps I was (again) able to use infix ASM instruction notation.

   Thank you,

On 7/15/2016 7:12 PM, Tim Northover wrote:
> On 15 July 2016 at 05:40, Alex Susu via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
>>      I am curious why did you changed TableGen to allow in principle only
>> writing ASM instructions in prefix notation. I ask because I personally use
>> an assembly notation that is infix (I could use a simple preprocessor that
>> changes prefix to infix).
> Running "git blame" points at
> https://github.com/llvm-mirror/llvm/commit/5ef1349, which gives the
> reasoning and suggests you ought to be able to set "HasMnemonicFirst".
> Tim.

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