[llvm-dev] Register interference

[Mark Schimmel via llvm-dev]

I have a case where I'd like to add an interference edge between a virtual register and a physical register. I have a class of GPR's. They are generally all allocable with any instruction, but there's one reg that can't be the destination of a load instruction. Instead of having to create a separate class that is a subset of GPR's minus the one reg I'd rather just add an interference. Is that possible? Consider the case where there are 3 such limited GPR's. Creating register classes becomes less attractive.

Thanks

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