[llvm-dev] BPF back end with vector operations - some strange error

[RCU via llvm-dev]

   Hi, Alexei,
     I used the BPF back end as a "template" in order to write my own back end, for a 
completely different architecture. But sure, I can provide you with hints how to add 
vector instructions to BPF itself.

     BTW, just curious, where is actually the BPF processor being used?

   Best regards,
     Alex


On 1/9/2016 9:37 PM, Alexei Starovoitov wrote:
> On Sat, Jan 9, 2016 at 11:29 AM, RCU via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
>>    Hello.
>>      I solved this issue (from the previous email).
>>
>>      Got inspired from
>> http://comments.gmane.org/gmane.comp.compilers.llvm.devel/73619, (also
>> https://groups.google.com/forum/#!topic/llvm-dev/LfltBGG9ru0),
>> http://lists.llvm.org/pipermail/llvm-dev/2007-April/008843.html
>>
>>      What I did was to edit ConnexInstrInfo.td and replaced all occurrences:
>>          PatLeaf<(imm)
>>         %(which were ambiguous since the variable name ("in dag operator")
>> does not have a type and this poses issues to the Type inference algorithm,
>> since I added in ConnexRegisterInfo.td a second RegisterClass with type
>> v2i64)
>>      with
>>          PatLeaf<(i64 imm)
>>      namely:
>>         - def i64immSExt32 : PatLeaf<(i64 imm),
>>                  [{return isInt<32>(N->getSExtValue()); }]>;
>>
>>    Best regards,
>>      Alex
>>
>>
>> On 1/8/2016 1:31 AM, RCU wrote:
>>>
>>>     Hello.
>>>       I've tried to add some simple arithmetic vector operations to the BPF
>>> backend
>>> available in the LLVM repo. Because I added in BPFRegisterInfo.td another
>>> RegisterClass
>>> (taken from the Mips backend):
>>>     def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128,
>>>                              (sequence "W%u", 0, 31)>;
>>> in order to support vector for example, ADD operations, I get the
>>> following error when
>>> building llc:
>>>     JEQ_ri:         (BPFbrcc i64:i64:$dst,
>>> (imm:i64)<<P:Predicate_i64immSExt32>>:$imm,
>>> (imm:{i64:v4i32})<<P:Predicate_BPF_CC_EQ>>, (bb:Other):$BrDst)
>>> Included from ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPF.td:14:
>>> ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPFInstrInfo.td:131:1: error: In
>>> JEQ_ri: Could
>>> not infer all types in pattern!
>>>     defm JEQ  : J<0x1, "jeq",  BPF_CC_EQ>;
>
> Great that you found a solution.
> Could you share what is the end goal for this vector instructions in BPF?
> Are you actually trying to extend BPF ISA and add kernel support for it?
> Or just using BPF backend as as a simplest/smallest playground?
> Regardless please share the patches when they're ready. I'm curious
> how you're adding vectorization. May be we can actually add them to kernel.
>