[llvm-dev] [GSoC 2016] Code Generation Improvements task

vivek pandya via llvm-dev llvm-dev at lists.llvm.org
Mon Feb 29 13:00:56 PST 2016

Hello LLVM Community,

I am interested doing following project with LLVM for GSoC 2016.

Code Generation Improvements:

Particularly Generalize target-specific backend passes that could be

I have done some initial study and try to understand the task to be done.
Please help me to develop the proposal.

Following are my initial findings :

1. lib/Target/Hexagon/RDF* :
Code for these pass is mostly target independent so to generalize them code
needs to be wrap in MachineFunction pass and then use it as required.
And if already not done , Merge Set of SSA based CFG can be computed at
time of SSA generation. This can improve performance of Ramakrishna’s

 2. lib/Target/AArch64/AArch64AddressTypePromotion.cpp
As far as I understand this pass promotes sign exertion for 32 bit integer
( address) and performs calculation on 64 bit number thus processes need
not switch execution mode to 32 bit.
Some other platforms such as MIPS, NVPTX, Sparc can be benefited by such
optimization because MIPS64 supports MIPS32 bit instruction and it requires
mode switch indicated by control register.  For PTX size of pointers
depends on the host machine so there might be similar situation.
But architectures like Power PC need not such optimization as 64 bit
instruction operating in 32 bit mode passes only lower 32 bits.

3. lib/Target/AArch64/AArch64PromoteConstant.cpp
This pass tries to simplify aggregate data like struct of const with
special SIMD instructions available on the system. For example on ARM its
NEON similarly other architectures have SIMD support specifically MIPS, IBM
System Z, Power PC with MMX/AltiVee and x86 with Intel’s AVX.

Apart from these , The proposal can include task for merging the delay slot
filling logic ( from Sparc and Mips ) into single target independent pass.

These is just a primary investigation. I am not expert with all
architectures supposed by LLVM but MIPS, x86 and to some extent ARM.

I have question regarding Target hooks. Does it means using TargetInfo an
SubTargetInfo class and at runtime decide architecture type and based on
that perform optimization ( i.e use target specific instructions ) ?

Please help me ! Am I going in right direction ? Suggest some code ,
document to look for further ideas. Also if any one like to mentor me for
this project.

Vivek Pandya
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