[llvm-dev] virtual registers
John Criswell via llvm-dev
llvm-dev at lists.llvm.org
Thu Feb 18 18:29:08 PST 2016
On 2/18/16 1:17 PM, Laura personen wrote:
> Thank you for your swift reply.
> I also need some reference about instruction sequence in llvm. I mean,
> do the order of instructions remain the same as they appear in a .ll
> file? or do they change by different optimizations (e.g. SSA-based
> Machine Code Optimizations
> Late Machine Code Optimizations
I believe there are optimizations that can change the order of
instructions at the LLVM IR level. You can find a list of LLVM
optimizations at http://llvm.org/docs/Passes.html.
When generating native code, the Instruction Scheduler will reorder the
native code instructions as well.
> If they change, which algorithms are used for reordering instructions?
> I appreciate a reference that explains them or just gives the name of
> the algorithms that are used.
You can look at the list of passes, but to get more detail, you will
probably need to examine the source code.
> On Thu, Feb 18, 2016 at 6:45 PM, John Criswell <jtcriswel at gmail.com
> <mailto:jtcriswel at gmail.com>> wrote:
> On 2/18/16 12:03 PM, Laura personen via llvm-dev wrote:
>> Is there any way to detect which virtual registers are assigned
>> to physical registers and which ones are assigned to memory slots?
> At the LLVM IR level, no. However, it might be possible for a
> MachineFunctionPass to determine this or to modify the register
> allocator to record this information somewhere for query by a
> MachineFunctionPass later.
> John Criswell
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
> John Criswell
> Assistant Professor
> Department of Computer Science, University of Rochester
Department of Computer Science, University of Rochester
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