[llvm-dev] Hexagon, inline assembly and packetization

Krzysztof Parzyszek via llvm-dev llvm-dev at lists.llvm.org
Wed Feb 17 13:35:53 PST 2016

On 2/17/2016 2:25 PM, Rail Shafigulin via llvm-dev wrote:
> I'm not very clear on how exactly does Hexagon handle inline assembly
> during packetization pass and afterwards. Say there are several
> instructions in inline assembly. Will Hexagon split them and packetize
> using dependencies? Will it create a packet for every instruction in the
> inline assembly? Would anyone be able to provide any insights.

Inline assembly is treated as a "solo" instruction in the packetizer.


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