[llvm-dev] Hexagon, inline assembly and packetization
Rail Shafigulin via llvm-dev
llvm-dev at lists.llvm.org
Wed Feb 17 12:25:36 PST 2016
I'm not very clear on how exactly does Hexagon handle inline assembly
during packetization pass and afterwards. Say there are several
instructions in inline assembly. Will Hexagon split them and packetize
using dependencies? Will it create a packet for every instruction in the
inline assembly? Would anyone be able to provide any insights.
Help is greatly appreciated.
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