[llvm-dev] Question about loading spilled register with fast register allocator

jingu kang via llvm-dev llvm-dev at lists.llvm.org
Thu Feb 11 01:59:54 PST 2016

Hi All,

I have a problem with loading spilled register. Let's look at the
simple example as follows:

Machine IR snippet:
ADD   --> it generates carry.
ADDC --> it uses carry.

The fast register allocator is enabled with "-O0" option and it
generates load instruction for one of ADDC's operands  spilled between
ADD and ADDC. When I eliminates the frame index for the load
instruction, the real offset of the frame index is bigger than load
instruction's immediate field and I generate add instruction in order
to make correct address for the stack slot. As a result, the carry bit
is broken. I think I could store and load carry bit with scratch
register or make a pass to force to reload register spilled at a
specific place. But I would like to check whether there are existing
ways or better ways to solve this problem. Could someone let me know
about it? If I missed something, please let me know.

JinGu Kang

More information about the llvm-dev mailing list