[llvm-dev] [RFC] Lanai backend

Jacques Pienaar via llvm-dev llvm-dev at lists.llvm.org
Tue Feb 9 09:40:21 PST 2016

Hi all,

We would like to contribute a new backend for the Lanai processor (derived
from the processor described in [1]).

Lanai is a simple in-order 32-bit processor with:
  * 32 32-bit registers, including:
    * 2 registers with fixed values;
    * 4 used for program state tracking (PC, SP, FP, RCA);
    * 2 reserved for explicit usage by user (R10 and R11), used in
threading library;
    * Up to 4 used for argument passing;
    * No callee-saved registers
  * No floating point support

Backend development is focused primarily on compiling C99 code (no
exception support). The patches implement all the parts required for code

* LLVM triple: http://reviews.llvm.org/D17003
* Clang support: http://reviews.llvm.org/D17002
* MCExpr & ELF: http://reviews.llvm.org/D17008
* Lanai backend (lib/Target/Lanai): http://reviews.llvm.org/D17011

We are still actively developing the backend and have many optimizations in

I'll be the maintainer of this backend.

Please leave code comments on the Phab patches, while discussing high-level
comments about the backend on this llvm-dev thread.



[1] David E. Culler, Anoop Gupta, and Jaswinder Pal Singh. 1997. Parallel
Computer Architecture: A Hardware/Software Approach (1st ed.). Morgan
Kaufmann Publishers Inc., San Francisco, CA, USA.
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