[llvm-dev] Assigning constant value without alloca/load/store

[Daniel Berlin via llvm-dev]

Because %val doesn't exist (really!).
In the actual IR, left hand sides do not exist.

The Value * (i32 1 in this case) is really linked directly into it's users
as a use.

So something like

declare foo(%a, %b)

%c = add  i32 %a, %b
%d = add i32 %ic, %a
ret i32 %d

really looks like this:


ret <operand points to add i32 <operand points to add i32 <operand points
to argument %a>, <operand points to argument %b>>, <operand points to
argument %a>>

To give a statement ordering and basic blocks, they are
intrusive-linked-list'd together into basic blocks.   But the LHS still
doesn't exist, even in that form.

There are no "declaration" operations, so you can't have an *instruction*
that is just a value itself because it's only point would be to produce an
LHS, and as we said, LHS's don't really exist.

Instead, because Value * supports both SSA values and constants, every user
would just have a use pointing to an i32 1 directly.

So in this case, the fake LHS abstraction llvm assembly provides is just
being exposed a bit.
In producing the IR, anything that isa<Constant>, you should just use
directly as an operand to wherever it needs to go.




On Mon, Feb 8, 2016 at 2:54 AM, Paul Peet via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> This looks much better than using "select i1 true, i32 1, i32 0".
> But since something like that (bitcast constant) is allowed why isn't it
> possible to simply do this:
> %val = i32 1
> ?
>
> 2016-02-08 7:45 GMT+01:00 David Majnemer <david.majnemer at gmail.com>:
>
>>
>>
>> On Sun, Feb 7, 2016 at 3:00 PM, Paul Peet via llvm-dev <
>> llvm-dev at lists.llvm.org> wrote:
>>
>>> Hello,
>>>
>>> I am currently trying to translate some custom IR to LLVM-IR and came
>>> across and issue.
>>> The custom IR has several registers and I am basically try to SSAfy it
>>> so it can be easily translated/converted to LLVM-IR.
>>>
>>> The problem:
>>>
>>> Since in my custom IR I can reassign every register I have to reassign
>>> every new expression with a new llvm Value. But my IR has something like
>>> this:
>>>
>>> REG A = VAR C + CONST 2
>>> REG A = CONST 12
>>>
>>> So my workaround looks like:
>>>
>>> ; I am returning the registers in an anonymous struct
>>> define { i32, i32, i32 } @test(i32 %var_c) {
>>>   ; Initializing registers
>>>   %reg_a_0 = select i1 true, i32 0, i32 0
>>>   %reg_b_0 = select i1 true, i32 0, i32 0
>>>   %reg_c_0 = select i1 true, i32 0, i32 0
>>>
>>>   ; Translated instructions
>>>   %reg_a_1 = add i32 %var_c, 2
>>>   %reg_a_2 = select i1 true, i32 12, i32 0
>>>
>>>   ; Prepare return values
>>>   %ret_0 = insertvalue { i32, i32, i32 } undef, i32 %reg_a_2, 0
>>>   %ret_1 = insertvalue { i32, i32, i32 } %ret_0, i32 %reg_b_0, 1
>>>   %ret_2 = insertvalue { i32, i32, i32 } %ret_1, i32 %reg_c_0, 2
>>>
>>>   ret { i32, i32, i32 } %ret_2
>>> }
>>>
>>> I am basically using "select i1 true, i32 1, i32 0" so after
>>> optimization it gets:
>>> %val = i32 1
>>>
>>> But as I said this looks like a hack to me and I can't simply use "%val
>>> = i32 1".
>>> So what's the proper way to do this without actually using
>>> alloca/load/store.
>>>
>>
>> You can use trivial bitcasts if you want to avoid load/store/alloca and
>> you want SSA variables for your constants:
>>   %val = bitcast i32 1 to i32
>>
>>
>>>
>>> Regards,
>>> Paul
>>>
>>> _______________________________________________
>>> LLVM Developers mailing list
>>> llvm-dev at lists.llvm.org
>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>
>>>
>>
>
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