[llvm-dev] New register class and patterns

Rail Shafigulin via llvm-dev llvm-dev at lists.llvm.org
Thu Feb 4 11:41:40 PST 2016

It does have an output register, it's just an implicit flag register. It
still has a DAG output. I'm not sure if the allocatable bit matters at this
point for selection purposes, but it does later. Not adding a type to the
register class can also be problematic (e.g. a flag register should have i1
added to regTypes for its class).


Does LLVM make an assumption that there is an implicit register output if
there are no outputs given to the pattern? I'm also curious about how did
LLVM know that an output of this instruction was setting a flag in a
special purpose register rather than a GPR? When I look at the DAG pattern
for the instruction, (Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond), I
can't find anything saying that it sets a flag in the special purpose

I'm reposting code for convenience.

def SDT_EscalaSetFlag      : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;

def Escalatflag     : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,

def Escala_CC_EQ  : PatLeaf<(imm),
                  [{return (N->getZExtValue() == ISD::SETEQ);}]>;

class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
  : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
           !strconcat(asmstr, "i\t$rA, $imm"),
           [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
  bits<5> op2;
  bits<5> rA;
  bits<16> imm;

  let Inst{25-21} = op2;
  let Inst{20-16} = rA;
  let Inst{15-0} = imm;

  let format = AFrm;
  let op2 = op2Val;

multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
  def _rr : SF_RR<op2Val, asmstr, Cond>;
  def _ri : SF_RI<op2Val, asmstr, Cond>;

defm SFEQ  : SF<0x0, "l.sfeq",  Escala_CC_EQ>;

Rail Shafigulin
Software Engineer
Esencia Technologies
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