[llvm-dev] Specifying DAG patterns in the instruction
Dylan McKay via llvm-dev
llvm-dev at lists.llvm.org
Mon Feb 1 15:53:44 PST 2016
Yes, that is exactly what it looks like.
On Tue, Feb 2, 2016 at 11:16 AM, Rail Shafigulin <rail at esenciatech.com>
> On Sat, Jan 30, 2016 at 5:32 PM, Dylan McKay <dylanmckay34 at gmail.com>
>> TableGen, as a DSL language, is made up of records. Every def
>> corresponds to a record. For example, TableGen has a class Register, and
>> your backend will define records by def GPR8 : Register<...>. You are
>> correct in saying that the record definition is one of the SDNode
>> values. These correspond 1:1 to llvm::ISD::NodeType
>> (DEF a, b) corresponds to
>> --------- a
>> A more complicated example, regarding that a and b themselves can be
>> nested DAGs.
>> --------- add
>> / \
>> / b
>> \ c
>> \ /
>> ---------- sub
>> And so on and so fourth.
> My next question is about the nodes of the Selection DAG. Based on what
> I'm seeing the nodes can either be registers or they can be instructions.
> If I understand correctly llvm::ISD::NodeType
> <http://llvm.org/docs/doxygen/html/namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110> tells
> me the type of the node (register, add instruction, pseudo instruction,
> What does a DAG set operation do? Does it create new node?
> Here is the example:
> (set GPR:$rD, (add (i32 GPR:$rA), (i32 GPR:$rB)))
> And here is what I assume this to look like:
> --------------- GPR:$rA
> GPR:$rd ----------- add
> --------------- GRP:$rb
> Am I correct?
> Any help is appreciated.
> Rail Shafigulin
> Software Engineer
> Esencia Technologies
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