[llvm-dev] Defining intrinsic with arbitrary number of parameter?

[Hongbin Zheng via llvm-dev]

Hi all,

Is there a way to define an intrinsic with arbitrary number of parameters,
but is not var_arg? For example, I want to define an intrinsic "llvm.foo"
such that I can overload it with two parameters:

i32 llvm.foo.i32.i32.i32(i32, i32)

And overload it with three parameters

i32 llvm.foo.i32.i32.i32.i32(i32, i32, i32)

Thanks a lot
Hongbin
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161219/e48d5db1/attachment.html>