[llvm-dev] Tablegen pattern matching question

Bhatu via llvm-dev llvm-dev at lists.llvm.org
Tue Aug 30 21:53:21 PDT 2016

Thanks for the information. Just a few more questions.

Does (i32 simm16:$im) mean casting $im to i32?
Do dags like (ValueType otherDag) correspond to separate SDNodes with
'otherDag' node as input? or do they just change the type annotation of the
'otherDag' node.

So I should have added the complete pattern. I'm trying to achieve rd = rd
+ imm. While reading the sparc backend code I came across the above casting
pattern and hence the confusion.
let Constraints = "$rd = $dst" in {
.. [(set R32:$rd, (add R32:$dst, simm16:$im) )]

Pratik Bhatu
Dual Degree(B.Tech + M. Tech), 5th Year
Computer Science and Engineering
IIT Hyderabad
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