[llvm-dev] Vector instruction legalization for v16i32 integer type when the only supported type is v32i16

Alex Susu via llvm-dev llvm-dev at lists.llvm.org
Tue Aug 9 16:21:44 PDT 2016

     I'm trying to implement an ADD operation for v16i32 vector register type when the 
only supported register type is v32i16.

     For doing this I am looking to implement in [MyTarget]ISelLowering.cpp, in 
LowerOperation() a custom operation lowering (and eventually operand type legalization). 
(For this I plan to follow an easy to understand example of custom lowering available at 
lib/Target/Mips/MipsISelLowering.cpp, SDValue 
MipsTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const.)

     The pseudocode of the algorithm I need to perform is something like this:
         Dest_v32i16 = Src1_v32i16 ADD Src2_v32i16
         ONE_v32i16 = 1
         IX_v32i16 = LDIX (load index of the Processing Element of the vector)
           IX_AND_v32i16 = IX_v32i16 AND 1 % and it with 1
             IX_AND_v32i16 == 0 % compare the result (each element of IX_AND_v32i16 with 0)
               WHERE true % if the result is true (if index of element is even)
                 WHERE CARRY % where add above gave a carry
                   Dest_v32i16 = Dest_v32i16 ADD ONE_v32i16

     In LowerOperation() I need to perform the right DAG.getNode() instantiations and 
"wirings" coresponding to the above algorithm in order to build a subDAG that is returned 
instead of the original SDNode.

     Please let me know if everything is OK.
     I would normally NOT do type legalization from v16i32 to v32i16 (no custom lower 
bitcasts) - but a previous thread arguments we have to (see 
http://lists.llvm.org/pipermail/llvm-dev/2016-January/094485.html: "Vectors of i16 are a 
bit special and we need to custom lower bitcasts to/from them. Therefore we do 
setOperationAction(ISD::BITCAST, VT, Custom)"...).

   Thank you,

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