[llvm-dev] X86ISelLowering: Promote 'add nsw' to a wider type

via llvm-dev llvm-dev at lists.llvm.org
Mon Aug 8 09:22:04 PDT 2016

> On Aug 8, 2016, at 8:22 AM, Artur Pilipenko via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> Hi Sanjay,
>> On 19 Jul 2016, at 18:54, Sanjay Patel <spatel at rotateright.com <mailto:spatel at rotateright.com>> wrote:
>> Hi Artur -
>> I don't think there's any reason to limit the transform to sexts only; that's just the case that was apparent in https://llvm.org/bugs/show_bug.cgi?id=20134 <https://llvm.org/bugs/show_bug.cgi?id=20134> , so I limited it to that pattern.
>> It's probably worth noting that I'm currently fighting through casts of all kinds in IR (InstCombine) rather than the backend:
> What is the current status of this work? Does it make sense to patch the existing code in X86ISelLowering in order to support looking through zext or the generic solution will be available soon?

As a side thought, this might be something best done in a CodeGenPrepare type position in the pipeline. The DAG is a little bit late because by that point you’ve lost some information (global information) and may not be able to eliminate all zexts/sexts accordingly. But instcombine may be a little bit early because it’ll hurt targets that prefer it the other way around. You could expand addressing mode stuff in CodeGenPrepare using knownbits or SCEV, maybe? We do something vaguely similar out of tree (but with the opposite goal, as our target only supports 32-bit offsets).

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