[llvm-dev] Variable in instruction mnemonic

[Sky Flyer via llvm-dev]

Hi all,

I would like to implement the conditional handling using predicate.
In tableGen, how is it possible to have variable in the start of the
instruction. In other words, an instruction definition starts with a
predicate variable!

considering ARM example:
let AsmString = !strconcat(*opc, "${p}", asm*);

having ARM example in mind and modifying it,
the AsmMatcherEmitter.cpp does not accept this pattern:

let AsmString = !strconcat(*"${p}", opc, asm*);

for instance: *ge add X Y*

With the latter pattern, LLVM complains that "error: Missing instruction
mnemonic".
My ASM dialect has this flavor and I wonder if it is possible to directly
generate it instead of modifying the output assembly file.

In general what do you suggest for defining/parsing mnemonics that are
consisting of two or three tokens and then followed by operands?

Cheers,
ES
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